The invention lies in the integrated technology field and relates, more specifically, to an integrated memory having memory cells and reference cells, and an operating method for such a memory.
U.S. Pat. Nos. 5,844,832 and 5,572,459 describe ferro-electric memories (FRAM or FeRAM), which have memory cells of the 1-transistor/1-capacitor type. The storage capacitor has a ferroelectric dielectric, whose polarization is set to different values in order to store different logic states. By setting the polarization of the dielectric, the capacitance of the storage capacitor is influenced. Since the aforementioned memory cells, during a read access, can effect only small potential changes on the bit lines connected to them because of their restricted capacity, these memories have differential read amplifiers, such as are also used, for example, in DRAMs (dynamic random access memories). Each read amplifier is connected to a pair of bit lines. During a read access to one of the memory cells, the latter is electrically connected via one of the bit lines to the associated read amplifier, while the other bit line of the pair of bit lines connected to this read amplifier connects a reference cell electrically to the second input of the read amplifier.
The reference cells are constructed in substantially the same way as the normal memory cells of the FRAM, and are used to generate a reference potential on the corresponding second bit line. The read amplifier then amplifies the potential difference which is established between the two bit lines. In order to generate the desired reference potential on the second bit line, it is necessary to store appropriate reference information previously in the reference cell. To this end, both in U.S. Pat. No. 5,572,459 and 5,844,832 the reference cells are modified as compared with the normal memory cells, in that they are connected via additional transistors to potential lines which are used to supply the desired reference information. These additional transistors are connected to a circuit node within the memory cell, the node being located between the respective selection transistor and the storage capacitor of the reference cell.
The aforementioned memory cells modified by means of an additional transistor have the disadvantage that, because of the transistor that is additionally present, they are not constructed fully identically with the normal memory cells. The result of this is that the reference cells are not produced on the same grid as the normal memory cells. This results in a more complicated manufacturing process for the memory.
It is accordingly an object of the invention to provide an integrated memory with memory cells and reference cells which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which whose memory cells and reference cells can be arranged in a regular grid. In addition, it is an object of the invention to specify an operating method for such a memory.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a first pair of bit lines and a plurality of word lines and reference word lines;
memory cells respectively arranged at crossing points of the word lines with a bit line of the first pair of bit lines and each having a selection switching element for connecting the memory cell with a respective bit line and the selection switching element having a control connection connected to a respective word line;
a first differential read amplifier connected to the bit lines of the first pair of bit lines and a second differential read amplifier;
two reference cells respectively arranged at a crossing point of one of the bit lines and a reference word line, having a structure substantially corresponding to a structure of the memory cells, and having a selection switching element for connecting the reference cells via a circuit node to a respective bit line, and the selection switching element having a control connection connected to the respective reference word line;
first switching elements connecting the circuit nodes to the read amplifier;
a first potential line for supplying a first potential to be stored in the reference cells;
second switching elements connecting the circuit nodes to the first potential line;
a second pair of bit lines connected to the second differential read amplifier and, in correspondence with the first pair of bit lines, having memory cells, reference cells, and first and second switching elements;
two third switching elements each connecting a respective one of the bit lines of the first pair of bit lines to a bit line of the second pair of bit lines; and
a second potential line connected to the circuit nodes of the bit lines of the second bit line pair via the second switching elements, the second potential line supplying a second potential to be stored in the reference cells of the second pair of bit lines.
In other words, the integrated memory has identically constructed memory cells and reference cells. The second switching elements are used to supply the reference information to the reference cells. Since the second switching elements are not connected to a circuit node within the reference cell but to a circuit node on the associated bit line, the reference cells do not have to be modified as compared with the reference cells. This permits, firstly, the production of the memory cell array having the memory cells and reference cells in a regular grid, whose extent is predefined by the minimum dimensions of the memory cells. Secondly, there results the advantage that writing and reading the reference information into and from the reference cells is carried out in the same way as the writing and reading of data into and from the memory cells. Since the precise behavior of the memory cells during an access also depends on fluctuations in the manufacturing process, the access behavior of the reference cells, which are constructed identically to the memory cells, is influenced in the same way, on account of such influences, as that of the memory cells. This therefore ensures that the reference information provided by the reference cells is matched to the changed access behavior of the normal memory cells, even for different manufacturing conditions of the memory.
In accordance with an added feature of the invention, the reference cells and the first switching elements are arranged at one end of the respective bit line opposite the read amplifier. This results in an arrangement which is advantageous in terms of circuitry, in which relatively few control signals are needed to drive the first switching elements. In order to maintain the grid of the cell array, the first switching elements can likewise be arranged in this grid.
According to another development of the invention, the first switching elements are arranged at the end of the respective bit line facing the read amplifier. This has the advantage that there is often sufficient space available in the read amplifiers, and the switching elements can therefore be arranged without problems, even if the grid of the memory cell array becomes very small because of very small memory cells.
In accordance with an additional feature of the invention, during a read access to a given one of the memory cells of one of the bit lines, the selection switching element of the given memory cell and the selection switching element of the reference cell of the other bit line are turned on and also both first switching elements are turned on and both second switching elements are turned off, and wherein, during a rewriting operation, carried out during the read access, of the information previously read out from the corresponding the memory cell by the read amplifier the selection switching elements of the given memory cell and of the reference cell are turned on and only the first switching element connected to the one bit line and the second switching element connected to the other bit line are turned on.
In accordance with a further feature of the invention, there is provided a control unit connected to the first and second potential lines, for generating the first and second potentials with respectively alternating levels.
With the above and other objects in view there is also provided, in accordance with the invention, an operating method for an integrated memory. The method comprises the following steps:
reading out information from two memory cells and transferring the information via two first bit lines to first inputs of two differential read amplifiers;
reading out reference information from reference cells and transferring the reference information via second bit lines to second inputs of the read amplifiers;
amplifying voltages present at the inputs of the read amplifiers with the read amplifiers;
disconnecting the reference cells from the read amplifiers;
connecting the reference cells to potential lines; and transferring potentials from the potential lines via the second bit lines to the reference cells.
In accordance with yet an added feature of the invention, the potentials of the potential lines are different, and the method comprises connecting the second bit lines to each other for setting a reference potential.
In accordance with a concomitant feature of the invention, the signals amplified by the read amplifiers are rewritten into the memory cells via the first bit lines, simultaneously with a transfer of the potentials into the reference cells via the second bit lines.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in Integrated memory having memory cells and reference cells, and operating method for such a memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.